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| technical note large current external fet contro ller type switching regulator dual-output, high voltage, high-efficiency step-down switching regulator (controller type) bd9011ekn , bd9011kv , bd9775fv overview the bd9011ekn/kv is a 2-ch synchronous controller with rect ification switching for enhanced power management efficiency. it supports a wide input range, enabling low power cons umption ecodesign for an array of electronics. features 1) wide input voltage range: 3.9v to 30v 2) precision voltage references: 0.8v 1% 3) fet direct drive 4) rectification switching for increased efficiency 5) variable frequency: 250k to 550khz (external synchronization to 550khz) 6) built-in selected off latch and aut o remove over current protection 7) built-in independent power up/power down sequencing control 8) make various application , step-down , step-up and step-up-down 9) small footprint packages: hqfn36v, vqfp48c applications car audio and navigation systems, crttv lcdtv pdptv stb dvd and pc systems portable cd and dvd players, etc. absolute maximum ratings (ta=25 ) parameter symbol rating unit parameter symbol rating unit extvcc voltage extvcc 34 *1 v comp1,2 voltage comp1,2 vreg5 v vcccl1,2 voltage vcccl1,2 34 *1 v det1,2 voltage det1,2 cl1,2 voltage cl1,2 34 v rt ? sync voltage rt ? sync sw1,2 voltage sw1,2 34 *1 v power dissipation pd 0.875 *2 hqfn36v w boot1,2 voltage boot1,2 40 *1 v boot1,2-sw1,2 voltage boot1,2-sw1,2 7 *1 v 1.1 *2 vqfp48c w stb, en1,2 voltage stb, en1,2 vcc v vreg5,5a vreg5,5a 7 v operating temperature topr -40 to +105 vreg33 vreg33 vreg5 v storage temperature tstg -55 to +150 ss1,2 ? fb1,2 ss1,2 ? fb1,2 vreg5 v junction temperature tj +150 *1 regardless of the listed rating, do not exceed pd in any circumstances. *2 mounted on a 70mm x 70mm x 0.8mm glass-epoxy board. de-rated at 7.44mw/ hqfn36v or 8.8 mw/ v qfp48c above 25 . apr.2008
2/28 operating conditions (ta=25 ) parameter symbol min. typ. max. unit input voltage 1 extvcc 3.9 *1 *2 12 30 v input voltage 2 vcc 3.9 *1 *2 12 30 v boot sw voltage boot sw 4.5 5 vreg5 v carrier frequency osc 250 300 550 khz synchronous frequency sync osc - 550 khz synchronous pulse duty duty 40 50 60 min off pulse tmin - 100 - nsec this product is not designed to prov ide resistance against radiation. *1 after more than 4.5v, voltage range. *2 in case of using less than 6v, short to vcc, extvcc and vreg5. electrical characteristics (unless otherwise specified, ta=25 vcc=12v stb=5v en1,2=5v ) parameter symbol limit unit conditions min. typ. max. vin bias current iin - 5 10 ma shutdown mode current ist - 0 10 a vstb=0v error amp block feedback reference voltage vob 0.792 0.800 0.808 v feedback reference voltage (ta=-40 to 105 ) vob+ 0.784 0.800 0.816 v ta=-40 to 105 open circuit voltage gain averr - 46 - db vo input bias current ivo+ - - 1 a fet driver block hg high side on resistance hghon - 1.5 - hg low side on resistance hglon - 1.0 - lg high side on resistance lghon - 1.5 - lg low side on resistance lglon - 0.5 - oscillator carrier frequency fosc 270 300 330 khz rt=100 k synchronous frequency fsync - 500 - khz rt=100 k ,sync=500khz over current protection block cl threshold voltage vswth 70 90 110 v cl threshold voltage ta=-40 to 105 vswth+ 67 90 113 v ta=-40 to 105 vreg block vreg5 output voltage vreg5 4.8 5 5.2 v iref=6ma vreg33 reference voltage vreg 33 3.0 3.3 3.6 v ireg=6ma vreg5 threshold voltage vreg_uvlo 2.6 2.8 3.0 v vreg:sweep down vreg5 hysteresis voltage dvreg_uvlo 50 100 200 mv vreg:sweep up soft start block charge current iss 6.5 10 13.5 a vss=1v charge current (ta=-40 to 105 ) iss+ 6 10 14 a vss=1v,ta=-40 to 105 note: not all shipped products are subject to outgoing inspection. 3/28 reference data (unless otherwise specified, ta=25 ) fig.1 efficiency 1 fig.4 reference voltage vs. temperature characteristics fig.5 over current detection vs. temperature characteristics fig.6 frequency vs. tem p erature characteristics 0 10 20 30 40 50 60 70 80 90 100 0123 output currentio[a] efficiency[%] 1.2v 1.8v 2.6v 3.3v 5.0v vin=12v 0.784 0.788 0.792 0.796 0.800 0.804 0.808 0.812 0.816 -40 -15 10 35 60 85 110 ambient temperature ta[] re fe renc e vol tag e vo b[ v] 60 70 80 90 100 110 -40 -15 10 35 60 85 110 ambient temperature ta[] ^??R vswth[mv] 270 280 290 300 310 320 330 -40 -15 10 35 60 85 110 ambient temperature ta[] osilating frequency f osc [khz] rt=100k 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 -40 -15 10 35 60 85 110 ambient temperature ta[] out put voltage vo[v] vreg5 vreg33 fig.7 internal reg vs. tem p erature characteristics 0 10 20 30 40 50 60 70 80 90 100 6 9 12 15 18 21 24 input voltage v in [v] efficiency[%] 3.3v 5.0v io=2a fig.2 efficiency 2 0 1 2 3 4 5 6 0 5 10 15 20 25 i nput voltag e v in [v] out put voltage vo[v] 3.3v 5.0v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0123456 output c urrent: i o [a] out put voltage vo[v ] loff= l loff=h r cl =15m fig.8 line regulation fig.9 load regulation 0 1 2 3 4 5 6 0246 input voltagev en [v] outputvoltage vo[v] 105 25 -40 fig.10 en threshold voltage fig.11 load transient response 1 fig.12 load transient response 2 0 1 2 3 4 5 6 0102030 input voltagev in [v] circ uitcurrent[ma] 105 25 -40 fig.3 circuit current v out v out i out i out 1a/div 50mv/div 1a/div 50mv/div 4/28 block diagram (parentheses indicate vqfp48c pin numbers) fig-13 pin configuration pin function table bd9011ekn hqfn36v fig-14 pin no. pin name function 1 sw1 high side fet source pin 1 2 dgnd1 low side fet source pin 1 3 outl1 low side fet gate drive pin 1 4 vreg5a fet drive reg input 5 vreg33 reference input reg output 6 fb1 error amp input 1 7 comp1 error amp output 1 8 ss1 soft start setting pin 1 9 det1 fb detector output 1 10 stb standby on/off pin 11 en1 output 1on/off pin 12 en2 output 2on/offpin 13 gnd ground 14 loff over current protection off latch function on/off pin 15 rt switching frequency setting pin 16 sync external synchronous pulse input pin 17 llm built-in pull-down resistor pin 18 det2 fb detector output 2 19 ss2 soft start setting pin 2 20 comp2 error amp output 2 21 fb2 error amp input 2 22 extvcc external power input pin 23 n.c. 24 vreg5 fet drive reg output 25 outl2 low side fet gate drive pin 2 26 dgnd2 low side fet source pin 2 27 sw2 high side fet source pin 2 28 outh2 hi side fet gate drive pin 2 29 boot2 outh2 driver power pin 30 cl2 over current detector setting pin 2 31 vcccl2 over current detection vcc2 32 vcc input power pin 33 vcccl1 over current detection vcc1 34 cl1 over current detector setting pin 1 35 boot1 outh1 driver power pin 36 outh1 high side fet gate drive pin 1 outh2 28 29 30 31 32 33 34 35 36 boot2 cl2 vcccl2 vcc vcccl1 cl1 boot1 outh1 det2 18 17 16 15 14 13 12 11 10 lmm sync rt loff gnd en2 en1 stb 1 2 3 4 5 6 7 8 9 sw1 dgnd1 outl1 vreg5a vreg33 fb1 comp1 ss1 det1 27 26 25 24 23 22 21 20 19 sw2 dgnd2 outl2 vreg5 extvcc fb2 comp2 ss2 tsd 5v reg 2.7v 3.3v reg tsd uvlo pw m comp err amp 0.8v sequence det uvlo fb2 ss2 comp2 det2 loff en2 en1 vreg5a extvcc stb vcc rt sync set q reset q reset set drv set reset vreg5 ocp uvlo tsd b.g sync osc slope pw m comp tsd uvlo q set reset drv set reset sw logic set q reset sequence det err amp 0.8v ocp slope gnd det1 sw logic outh1 sw1 outl1 dgnd1 ss1 comp1 boot1 cl1 vcccl1 vreg33 fb1 5(19) 17(35) 16 (34) 32 (7) 9 (24) 21(39) 24(44) 19(37) 26(47) 33(8) 1(13) 34(10) 36(12) 4(17) 3(15) 2(14) 8(23) 6(21) 7(22) 35(11) 30(3) 31(5) 29(2) 28(1) 27(48) 20(38) 25(46) 22 (41) 10 (25) 15 (33) 13 (29) 11 (26) 12 (27) 14 (31) 18 (36) (30) (gnds) llm 5/28 40 41 42 43 44 45 46 47 48 36 35 34 33 32 31 30 29 28 1 2 3 4 5 6 7 8 9 10 11 12 outh2 boot2 cl2 n.c vcccl2 n.c vcc vcccl1 n.c cl1 boot1 outh1 21 20 19 18 17 16 15 14 13 24 23 22 fb1 n.c vreg33 n.c vreg5a n.c outl1 dgnd1 sw1 det1 ss1 comp1 27 26 25 37 38 39 n.c extvcc n.c n.c vreg5 n.c outl2 dgnd2 sw2 ss2 comp2 fb2 det2 llm sync rt loff gnds gnd n.c en2 en1 stb n.c pin configuration pin function table bd9011kv vqfp48c fig-15 block functional descriptions ? error amp the error amp compares output feedback voltage to the 0.8v refer ence voltage and provides the comparison result as comp voltage , which is used to determine the switching duty. comp voltage is limited to the ss voltage, since soft start at power up is based on ss pi n voltage. ? oscillator (osc) oscillation frequency is determined by the switching frequency pin (rt) in this block. the frequency can be set between 250khz and 550khz. ? slope the slope block uses the clock produced by the oscillator to genera te a triangular wave, and sends the wave to the pwm comparat or. ? pwm comp the pwm comparator determines switching duty by comparing the comp voltage, output from the error amp, with the triangular wave from the slope block. switching duty is limited to a percentage of the in ternal maximum duty, and thus cannot be 100% of the maximum. ? reference voltage (5vreg 33vreg) this block generates the internal reference voltages: 5v and 3.3v. ? external synchronization (sync) determines the switching frequency, based on the external pulse applied. ? over current protection (ocp) over current protection is activated when the vcccl-cl voltage re aches or exceeds 90mv. when over current protection is active, duty is low, and output voltage also decreases. when loff=l, the output voltage has fallen to 70% or below and output is latched off. the of f latch mode ends when the latch is set to stb, en. ? sequence control (sequence det) compares fb voltage with reference voltage (0.56v) and outputs the result as det. ? protection circuits (uvlo/tsd) the uvlo lock out function is activated when vreg falls to about 2.8v, while tsd turns outputs off when the chip temperature re aches or exceeds 150 . output is restored when temperature falls back below the threshold value. pin no. pin name function 1 outh2 high side fet gate drive pin 2 2 boot2 outh2 driver power pin 3 cl2 over current detection pin 2 4 n.c non-connect (unused) pin 5 vcccl2 over current detection vcc2 6 n.c non-connect (unused) pin 7 vcc input power pin 8 vcccl1 over current detection cc1 9 n.c non-connect (unused) pin 10 cl1 over current detection setting pin 1 11 boot1 outh1 driver power pin 12 outh1 high side fet gate drive pin 1 13 sw1 high side fet source pin 1 14 dgnd1 low side fet source pin 1 15 outl1 low side fet gate drive pin 1 16 n.c non-connect (unused) pin 17 vreg5a fet drive reg input 18 n.c non-connect (unused) pin 19 vreg33 reference input reg output 20 n.c non-connect (unused) pin 21 fb1 error amp input 1 22 comp1 error amp output 1 23 ss1 soft start setting pin 1 24 det1 fb detector output 1 25 stb standby on/off pin 26 en1 output 1 on/off pin 27 en2 output 2 on/off pin 28 n.c non-connect (unused) pin 29 gnd ground 30 gnds sense ground 31 loff over current protection off latch function on/off pin 32 n.c non-connect (unused) pin 33 rt switching frequency setting pin 34 sync external synchronous pulse input pin 35 llm built-in pull-down resistor pin 36 det2 fb detector output 2 37 ss2 soft start setting pin 2 38 comp2 error amp output 2 39 fb2 error amp input 2 40 n.c non-connect (unused) pin 41 extvcc external power input pin 42 n.c non-connect (unused) pin 43 n.c non-connect (unused) pin 44 vreg5 fet drive reg output 45 n.c non-connect (unused) pin 46 outl2 low side fet gate drive pin 2 47 dgnd2 low side fet source pin 2 48 sw2 high side fet source pin 2 6/28 application circuit example (parentheses indicate vqfp48c pin numbers) fig-16a step-down cout=os capacitor there are many factors(the pcb board layout, output curr ent, etc.)that can affect t he dcdc characteristics. please verify and confirm using practical applications. fig-16b step-down cout=ceramic capacitor there are many factors(the pcb board layout, output curr ent, etc.)that can affect t he dcdc characteristics. please verify and confirm using practical applications. sw1 dgnd1 outl1 vreg5a vreg33 fb1 comp1 ss1 det1 stb en1 en2 gnd loff rt sync llm sw2 det2 dgnd2 outl2 vreg5 extvcc fb2 comp2 ss2 outh1 boot1 cl1 vcccl1 vcc vcccl2 cl2 boot2 outh2 100k 0.1uf 1uf 1uf 39k 15000pf 0.1uf 0.33 uf 10 15m 15m 0.33uf 1uf 39k 15000pf 15k 47k 220uf ( os ?? ) 220uf (os ?? ) 13k 68k 10uh vo(5v/3a) rb051 l-40 rb051 l-40 10uh vo(3.3v/3a) sp8k2 sp8k2 vin(12v) 31 (5) 27 (48) 0.1 uf 0.1 uf 36 (12) 35 (11 ) 32 (7) 30 (3) 29 (2) 28 (1) 26 (47) 24 (44) 22 (41) 21 (39) 20 (38) 19 (37) 18 (36) 17 (35) 16 (34) 15 (33) 14 (31) 13 (29) 12 (27) 11 (26) 10 (25) 1 (13) 3 (15) 4 (17) 5 (19) 6 (21) 7 (22) 9 (24) 2 (14) 25 (46) 8 (23) 23 100 1nf 1nf 100 rb160 va-40 rb160 va-40 33 (8) 34 (10) 100uf (slf12565 tdk) (slf12565 tdk) sw1 dgnd1 outl1 vreg5a vreg33 fb1 comp1 ss1 det1 stb en1 en2 gnd loff rt sync llm sw2 det2 dgnd2 outl2 vreg5 extvcc fb2 comp2 ss2 outh1 boot1 cl1 vcccl1 vcc vcccl2 cl2 boot2 outh2 0.1uf 1uf 1uf 1k 10000pf 0.1uf 0.33 uf 10 23m 23m 0.33uf 1uf 3.3k 3300pf 20k 43 k 12k vo(1.8v/2a) rb051 l-40 rb051 l-40 10uh vo(2.5v/2a) sp8k2 sp8k2 vin(12v) 31 (5) 27 (48) 0.1 uf 0.1 uf 36 (12) 35 (11 ) 33 (8) 32 (7) 30 (3) 29 (2) 28 (1) 26 (47) 24 (44) 22 (41) 21 (39) 20 (38) 19 (37) 18 (36) 17 (35) 15 (33) 14 (31) 13 (29) 1 (13) 3 (15) 4 (17) 5 (19) 6 (21) 7 (22) 9 (24) 2 (14) 25 (46) 8 (23) 23 100 1nf 1nf 100 330pf 15k 150 3300pf 330pf 1000pf 510 10uh rb160 va-40 rb160 va-40 34 (10) 100uf 100k 16 (34) 12 (27) 11 (26) 10 (25) 30uf (c2012jb 0j106k tdk) 30uf (c2012jb 0j106k tdk) (slf10145 tdk) (slf10145 tdk) 7/28 fig-16c step-down low input voltage there are many factors(the pcb board layout, output curr ent, etc.)that can affect t he dcdc characteristics. please verify and confirm using practical applications. fig-16d step-up and step-up-down there are many factors(the pcb board layout, output curr ent, etc.)that can affect t he dcdc characteristics. please verify and confirm using practical applications. vo(12v/1a) 18 (36) 17 (35) 15 (33) 14 (31) 13 (29) 3300pf 10k sw1 dgnd1 outl1 vreg5a vreg33 fb1 comp1 ss1 det1 stb en1 en2 gnd loff rt sync llm sw2 det2 dgnd2 outl2 vreg5 extvcc fb2 comp2 ss2 outh1 boot1 cl1 vcccl1 vcc vcccl2 cl2 boot2 outh2 0.1uf 1uf 1uf 10k 22000pf 0.1uf 0.33 uf 10 10m 10m 0.33uf 1uf 4.7k 22000pf 6.2k 91 k 220uf 23.5k vo(24v/1a) 27uh sp8k2 vin(12v) 27 (48) 1uf 0.1 uf 36 (12) 35 (11 ) 32 (7) 29 (2) 28 (1) 26 (47) 24 (44) 22 (41) 21 (39) 20 (38) 19 (37) 1 (13) 3 (15) 4 (17) 5 (19) 6 (21) 7 (22) 9 (24) 2 (14) 25 (46) 8 (23) 23 100 1nf 1nf 100 1000pf 680 k 5.1k 1000pf 1000pf 220 uf regspic tm 27uh rss 065n03 co1 rb051l-40 l1 100uf 34 (10) 33 (8) 30 (3) 31 (5) rb160 va-40 rb051 l-40 co2 l2 do3 100k 16 (34) 12 (27) 11 (26) 10 (25) (slf12565 tdk) (slf12565 tdk) regspic tm is trade mark of rhom sw1 dgnd1 outl1 vreg5a vreg33 fb1 comp1 ss1 det1 stb en1 en2 gnd loff rt sync llm sw2 det2 dgnd2 outl2 vreg5 extvcc fb2 comp2 ss2 outh1 boot1 cl1 vcccl1 vcc vcccl2 cl2 boot2 outh2 0.1uf 1uf 1uf 3.3k 4700pf 0.1uf 0.33 uf 10 23m 23m 0.33uf 1uf 10k 2200pf 20k 12k vin(5v) 31 (5) 27 (48) 36 (12) 35 (11 ) 33 (8) 32 (7) 30 (3) 29 (2) 28 (1) 26 (47) 24 (44) 22 (41) 21 (39) 20 (38) 19 (37) 18 (36) 17 (35) 15 (33) 14 (31) 13 (29) 1 (13) 3 (15) 4 (17) 5 (19) 6 (21) 7 (22) 9 (24) 2 (14) 25 (46) 8 (23) 23 100 1nf 1nf 100 100pf 33pf 43 k 30uf ( ???? ) rb051 l-40 6.8uh vo(2.5v/2a) sp8k2 1000pf 300 34 (10) 100uf 100k 16 (34) 12 (27) 11 (26) 10 (25) rb160 v a -40 30uf ( ???? ) vo(1.8v/2a) rb051 l-40 sp8k2 15k 100 3300pf 6.8uh 0.1uf rb160 va-40 0.1uf (slf10145 tdk) (slf10145 tdk) 8/28 vcc-vout vout l vcc f il = [a] ??? 5 vcc-vout vout il vcc f l = [h] ??? 7 fig-17 vout vcc - vout vcc irms = iout [a] ?? ? 10 application component selection (1) setting the output l value the coil value significantly influences the output ripple current. thus, as seen in equation (5), the larger the coil, and the higher the switching frequency, the lowe r the drop in ripple current. the optimal output ripple current setting is 30% of maximum current. il = 0.3 ioutmax.[a] ??? 6 il output ripple current f switching frequency outputting a current in excess of the coil current rating will cause magnetic saturation of the coil and decrease efficiency. please establish sufficient margin to ensure that peak current does not exceed the coil current rating. use low resistance (dcr, acr) coils to minimize coil loss and increase efficiency. (2) setting the output capacitor co value select the output capacitor with the highest value for ripple voltage (v pp ) tolerance and maximum drop voltage (at rapid load change). the following equation is used to determine the output ripple voltage. i l vo 1 step down v pp = i l r esr + [v] note: f switching frequency co vcc f be sure to keep the output co setting within the allowable ripple voltage range. please allow sufficient output voltage margin in establishing the capacitor rating. note that low-esr capacitors enable lower output ripple voltage. also, to meet the requirement for setting t he output startup time parameter within th e soft start time range, please factor in the conditions described in the capacitance equation (9) for output capacitors, below. tss (limit ? iout) tss soft start time co Q ??? 9 vout ilimit over current detection value 2/16 reference note: less than optimal capacitance values may cause problems at startup. (3) input capacitor selection the input capacitor serves to lower the output impedance of the power source connected to the input pin (vcc). increased power supply output impedance can cause input voltage (v cc) instability, and may negatively impact oscillation and ripple rejecti on characteristics. therefore, be certain to establish an input capacitor in close proximity to the vcc and gnd pins. select a low-esr capacitor with the required ripple current capacity and the capability to withstand temperature changes without wide tolerance fluctuations. the ripple current irmss is determined using equation (10). also, be certain to ascertain the op erating temperature, load range and mosfet conditions for the application in which the capacitor will be used, since capacitor performance is heav ily dependent on the application?s input power characteristics, subs trate wiring and mosfet gate drain capacity. l vin vout co cin i l output ripple current i l vcc co l vout fig-18 input capacitor fig-19 9/28 vo r8 r9 internal ref. 0.8v fb (4) feedback resistor design please refer to the following equation in determining the pro per feedback resistance. the recommended setting is in a range between 10k and 330k . resistance less than 10k risks decreased power efficiency, while setting the resistance value higher than 330k will result in an internal error amp input bias current of 0.2ua increasing the offset voltage. r8 +r9 vo = 0.8 [v] ??? 11 r9 fig-20 (5) setting switching frequency the triangular wave switching frequency can be set by connecting a resistor to the rt 15(33) pin. the rt sets the frequency by adjusting the charge/discharge current in relation to the inte rnal capacitor. refer to the figure below in determining prope r rt resistance, noting that the recommended resistance setting is between 50k and 130k . settings outside this range may render the switching function inoperable, and proper oper ation of the controller over all cannot be guaranteed when unsupported resistance values are used. 250 300 350 400 450 500 550 50 60 70 80 90 100 110 120 130 rt [ k] ? [ khz ] fig-21 rt vs. switching frequency (6) setting the soft start delay the soft start function is necessary to prevent an inrush of coil current and output voltage over shoot at startup. the figure below shows the relation between soft start delay time and capacitance, which can be calculated using equation (12) at right. 0.8v(typ.) css tss = [sec] ??? (12) iss(10 a typ.) fig-22 ss capacitance vs. delay time recommended capacitance values are between 0.01uf and 0. 1uf. capacitance lower than 0.01uf may generate output overshoots. please use high accuracy components (such as x5r) when implementing sequential startups involving other power sources. be sure to test the actual devices and applicat ions to be used, since the soft start time varies, depending on input voltage, output voltage and capaci tance, coils and other characteristics. 0.01 0.1 1 10 0.001 0.01 0.1 ss capacitance[uf] delay time[ms] 10/28 over current detection point i l a comp fb c r feedback l vin i l vo vcccl cl rcl -18 0 -9 0 0 90 18 0 a 0 0 -90 -180 (a) gbw(b) -180 phase margin -90 -20db/decade gain [db] phase [deg] 1 2 rca point (a) fa = 1.25[hz] 1 2 rc point (b) fa = gbw [hz] (7) setting over current detection values the current limit value ilimit is determined by the resistance of the rcl established between cl and vcccl. 90m ilimit = [a] ??? (13) rcl fig-23 fig-24 there are 2 current limit functi on (on/off control type and off latch type) toggled by loff pin. ? loff=l (0 12/28 vo1 vcc vreg5 vreg5 outh1 boot1 vcc boot2 sw1 outl1 dgnd1 fb1 vo2 comp1 ss1 det2 outh2 outl2 sw2 dgnd2 fb2 comp2 ss2 det1 stb en1 en2 gnd 9 mosfet selection fet uses nch mos ? v ds vcc ? v gsm1 boot-sw interval voltage ? v gsm2 vreg5 ? allowable current voltage current + ripple current should be at least the over current protection value select a low on-resistance mosfet for highest efficiency fig-33 10 schottky barrier diode selection ? reverse voltage v r vcc ? allowable current voltage current + ripple current should be at least the over current protection value select a low forward voltage, fast recovery diode for highest efficiency ? the shoot-through may happen when the input parasitic capacitance of fet is extremely big or the duty ratio is less than or equal to 10%. less than or equal to 1000pf input parasitic capacitance is recommended. please confirm operation on the actual application since this character is affected by pcb layout and components. 11 sequence function circuit diagram timing chart fig-35 fig-36 v cc i l vo v ds v gsm1 v gsm2 v ds v cc vo v r with en1, 2 at ?h? level, when en1 goes ?l?, vo1 turns off, but vo2 output continues. when en1 stays ?h? and en2 returns to ?h?, det1 is in open state; thus ss2 is asserted, and vo2 output starts. if vo2 is 76% of the voltage setting or higher, det2 goes open and ss1 is asserted, starting vo1 output. en1 en2 det2 ss1 fb1 vo1 det1 ss2 fb2 vo2 0.61v over 76% under 70% 0.56v 0.61v 0.56v over 76% over 70% with en1,2 at ?h? level, i f vo1 starts at 76% or more o f voltage setting, det goes open and ss1 is asserted, starting vo2 output. same as ?a? at left a with en2 set ?l?, if vo2 goes below 70% the voltage setting, det2 shorts and ss1 is asserted, turning vo1 off a fig-34 13/28 input/output equivalent circ uits (items in parentheses apply to vqfp48c) 1(13) 27(48)pin sw1 sw2 29(2) 35(11)pin boot2 boot1 28(1) 36(15)pin outh1 outh2 2(14) 26(47)pin dgnd1 dgnd2 3(15) 25(46)pin outl1 outl2 24(44) vreg5 / 4(17)vreg5a 14(31)pin loff 16(34)pin sync 6(21) 21(39)pin fb1 fb2 8(23) 19(37)pin ss1 ss2 10(25) 11(26) 12(27)pin stb en1 en2 9(24) 18(36)pin det1 det2 15(33)pin rt 17(35)pin llm 30(3) 34(10)pin cl2 cl1 31(5) 33(8)pin vcccl2 vcccl1 7(22) 20(38)pin comp1 comp2 22(41)pin extv cc 24(44)pin vreg5 5(19)pin vreg33 4(17)din vreg5a boot outh sw 300k outl dgnd loff 100k 135.8k 172.2k vreg5 fb vreg5 / vreg5a 1k 2.5k ss vreg5 / vreg5a 100k 50k 2k vcc stb en 172.2k 135.8k 100k det vreg5 / vreg5a 10k vreg5 rt sync 5k 250k vreg5 1p vreg5a llm 308k comp vreg5 / vreg5a 20 5k 5k vcc vreg5a extvcc vreg5 vcc vcc 150k 746.32k 255k vreg33 vreg5a vcc 150k 746.32k 469.06k vcccl vcc cl 5k 5p vcc 1k 14/28 n p + (pina) resistor parasitic element p p + gnd p n operation notes 1 absolute maximum ratings exceeding the absolute maximum ratings for supply voltage, operating temperature or other parameters can damage or destroy the ic. when this occurs, it is impossible to identify the source of the damage as a short circuit, open circuit, etc. therefore, if any special mode is bei ng considered with values expected to exceed absolute maximum ratings, consider taking physical safety measures to protect the circuits, such as adding fuses. 2 gnd electric potential keep the gnd terminal potential at the lowest (mi nimum) potential under any operating condition. 3 thermal design be sure that the thermal design allows sufficient margin for power dissipation (pd) under actual operating conditions. 4 inter-pin shorts and mounting errors use caution when positioning the ic for mounting on printed surf ace boards. connection errors may result in damage or destruction of the ic. the ic can also be damaged when fore ign substances short output pi ns together, or cause shorts between the power supply and gnd. 5 operation in strong el ectromagnetic fields use caution when operating in the presence of strong electromagnetic fields, as this may cause the ic to malfunction. 6 testing on application boards connecting a capacitor to a low impedance pin for testing on an application board may subject the ic to stress. be sure to discharge the capacitors after every test process or step. alwa ys turn the ic power supply off before connecting it to or removing it from any of the apparatus us ed during the testing process. in addition, ground the ic during all steps in the assembly process, and take similar antistatic pr ecautions when transporting or storing the ic. 7) the output fet the shoot-through may happen when the input parasitic capacitance of fet is extremely big or the duty ratio is less than or equal to 10%. less than or equal to 1000pf input parasi tic capacitance is recommended. please confirm operation on the actual application since this character is affected by pcb layout and components. 8 this monolithic ic contains p+ isolation and p substrate layers between adjacent elements in order to keep them isolated. p-n junctions are formed at the intersection of these p layers wi th the n layers of other elements, creating a parasitic diode or transistor. relations between each potential may form as sh own in the example below, where a resistor and transistor are connected to a pin: with the resistor, when gnd pin a, and with the transistor (npn), when gnd pin b: the p-n junction operates as a parasitic diode with the transistor (npn), when gnd pin b: the p-n junction operates as a parasitic transistor by intera cting with the n layers of elements in proximity to the parasitic diode described above. parasitic diodes inevitably occur in the structure of the ic. t heir operation can result in mut ual interference between circuit s, and can cause malfunctions, and, in turn, physical damage or dest ruction. therefore, do not employ any of the methods under which parasitic diodes can operate, such as applying a voltage to an input pin lower than the (p substrate) gnd. fig-37 fig-38 fig-39 fig-40 9 gnd wiring pattern when both a small-signal gnd and high curr ent gnd are present, single-point gr ounding (at the set standard point) is recommended, in order to separate the small-signal and high current patterns, and to be sure voltage changes stemming from the wiring resistance and high current do not cause any voltage change in the sma ll-signal gnd. in the same way, care must be taken to avoid wiring pattern fluctuati ons in any connected external component gnd. (pinb) transistor npn p + p + n n p substrate gnd n p c e b parasitic element or transistor gnd c b parasitic element or transisto r (pinb) e (pina) parasitic element 15/28 10 in some application and process testing, vcc and pin potential may be reversed, possi bly causing internal circuit or element damage. for example, when the external capacitor is charged, t he electric charge can cause a vcc short circuit to the gnd. in order to avoid these problems, lim iting output pin capacitance to 100 f or less and inserting a vcc series countercurrent prevention diode or bypass diode between the various pins and the vcc is recommended. fig-41 11 thermal shutdown (tsd) this ic is provided with a built-in thermal shutdown (t sd) circuit, which is designed to prevent thermal damage to or destruction of the ic. normal operation should be within the power dissipation parameter, but if the ic should run beyond allowable pd for a continued period, junction temperature (tj) will rise, thus activating the tsd circuit, and turning all outp ut pins off. when tj again falls below the tsd threshold, circui ts are automatically restored to normal operation. note that the tsd circuit is only asserted beyond the absolute maximu m rating. therefore, under no circumstances should the tsd be used in set design or for any purpose ot her than protecting the ic against overheating 12 the sw pin when the sw pin is connected in an application, its coil count er-electromotive force may give rise to a single electric potential. when setting up the applicatio n, make sure that the sw pin never exceeds the absolute maximum value. connecting a resistor of several will reduce the electric potential. (see fig. 43) fig-42 13 dropout operation when input voltage falls below approximately output voltage / 0.9 (varying depending on operating frequency) the on interval on the outl side mos is lost, making boost applicat ions and wrap operation impossible. if a small differential between input and output voltage is envision ed for a prospective application, connec t the load such that the sw voltage drops to the gnd level. managing this load requires discharg ing the sw line capacitance (sw pin capacitance: approx. 500pf; outl side mos d-s capacitance; schottky capacitanc e). supported loads can be ca lculated using the equation below. output voltage sw line capacitance iload = 25n note that sw line capacitance is lower with smaller loads, and more stable operation is attained when low voltage bias circuits are configured as in the example below (fig. 44). however, the degree to which line capacitance is reduced or operational stability is attained will vary depending on the board layout and components. theref ore, be certain to confirm the effectiveness of these desi gn factors in actual operation before entering mass production. fig-43 vcc pin bypass diode countercurrent prevention diode out sw vcc vcc vreg vo out boot dgnd outl outh sw r vcc vo 16/28 hqfn36v 0.0 0.2 0.4 0.6 0.8 1.0 0 25 50 75 100 125 150 ambient temperatoreta [] power dissipationpd [w] pd(w) 0.875w 0.56w vqfp48c 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 25 50 75 100 125 150 ambient temperatoreta [] power dissipationpd [w] pd(w) 1.1w 0.75w power dissipation vs. temperature characteristics ? stand-alone ic ? stand-alone ic ? mounted on rohm standard board ? mounted on rohm standard board 70mm x 70mm x 1.6mm glass-epoxy board 70mm 70mm 1.6mm glass-epoxy board part order number b d 9 0 1 1 k v e 2 rohm part code type/no. package type kv vqfp48c ekn hqfn36v hqfn36v unit:mm 17/28 description bd9775fv,bd9011ekn/kv is switching controller with synchronous rectification( bd9775fv is 1channel synchronous rectification, bd9011ekn/kv is 2channel sy nchronous rectification.) an d wide input range. it can contribute to ecological design(lower power consumption) for most of electronic equipments. bd9775fv (1channel synchronous rectification configuration) features (bd9775fv) 1) 2channel step-down dc/dc fet driver 2) synchronous rectification for channel 2 3) able to synchronize to an external clock signal 4) over current protection (ocp) by monitoring vds of p channel fet 5) short circuit protection (scp) by delay time and latch method 6) under voltage lock out (uvlo) 7) thermal shut down (tsd) 8) package : ssop-b28 applications (bd9775fv) car navigation system, car audio, display, flat tv absolute maximum ratings (ta=25 )(bd9775fv) parameter symbol limits units supply voltage (vcc to gnd) vcc 36 v vref to gnd voltage vref 7 v vrega to gnd voltage vrega 7 v vregb to vcc voltage vregb 7 v out1, out2h to vcc voltage vouth 7 v out2l to gnd voltage voutl 7 v power dissipation pd 640(*1) mw operating temperature range topr -40 to +85 storage temperature range tstg -55 to +125 junction temperature tjmax +125 (*1) without heat sink, reduce to 6.4mw when ta=25 or above pd is 850mw mounted on 70x70x1.6mm, and reduce to 8.5mw/ above 25 . 18/28 recommended operating conditions ta=-25 to +75 (bd9775fv) electrical characteristics ta = 2 5 vcc=13.2v, fosc=100khz, ctl1=3v, ctl2=3v (bd9775fv) parameter symbol limits unit condition min. typ. max. whole device stand-by current iccst 5 a ctl1,ctl2=0v circuit current icc 2.5 4.2 7 ma fb1,fb2=0v reference voltage vref output voltage vref 2.97 3.00 3.03 v io=-1ma line regulation dvli 10 mv vcc=7 to 18v,io=-1ma load regulation dvlo 10 mv io=-0.1ma to -2ma short output current ios -60 -22 -5 ma internal voltage regulator vrega output voltage vrega 4.5 5. 0 5.5 v switching with cout=5000pf vregb output voltage vregb vcc-5.5 vcc- 5.0 vcc-4.5 v switching with cout=5000pf vregb dropout voltage vdregb 1.8 2.2 v vregb to gnd voltage oscillator oscillating frequency fosc 90 100 110 khz rt=27k ,ct=470pf frequency tolerance dfosc 2 % vcc=7 to 18v synchronized frequency synchronized frequency osc2 120 khz fin=120khz fin threshold voltage vthfin 1.2 1.4 1.6 v fin input current ifin -1 1 a vfin=1.4v error amplifier threshold voltage vthea 0.98 1.00 1.02 v inv input bias current ibias -1 1 a voltage gain av 70 db dc band width bw 2.0 mhz av=0db maximum output voltage vfbh 2.2 2.4 2.6 v inv=0.5v minimum output voltage vfbl 0.1 v inv=1.5v output sink current isink 0.5 2 5.2 ma fb1,2 terminal output source current isource1 -170 -110 -70 a fb1 terminal isource2 -200 -130 -85 a fb2 terminal parameter symbol limits units min typ max supply voltage vcc 6.0 - 30.0 v oscillating frequency osc 30 100 300 khz timing resistance rt 10 27 56 k timing capacitance ct 100 470 4700 pf 19/28 parameter symbol limits unit condition min. typ. max. pwm comparator threshold voltage at 0% vth0 0. 88 0.98 1.08 v fb voltage threshold voltage at 100% vth100 1.88 1.98 2.08 v fb voltage dtc input bias current idtc -1 1 a fet driver sink current isink 20 36 58 ma vds=0.4v source current isource -510 -320 -180 ma vds=0.4v on resistance ronn 7.0 11.0 17.8 out1,2h,2l : l ronp 0.7 1.4 2.2 out1,2h,2l : h rise time tr 20 nsec switching with cout=5000pf fall time tf 100 nsec switching with cout=5000pf driver?s duty cycle of synchronous rectification duty 42 45 48 % rsync=30k , 50% of main driver?s duty cycle sync terminal voltage vsync 1.45 1.55 1.65 v rsync=30k ,fb=1.5v over current protection (ocp) vs threshold voltage vths vcc-0.24 vcc-0.21 vcc-0.18 v rcl=21k , the output tern off after detected 8 cycle vs input current ivsh -1 1 a vs1,vs2=pbu ivsl -1 1 a vs1,vs2=0v cl input current icl 9 10 11 a stand-by threshold voltage vctl 1.0 1.5 2.0 v cl input current ictl 6 15 30 a ctl1,ctl2=3v short circuit protection scp timer start voltage vtime 0.6 0.7 0.8 v inv voltage threshold voltage vthscp 1.92 2.00 2.08 v scp voltage stand-by voltage vstscp 10 100 mv scp voltage source current isoscp -4.0 -2.5 -1.5 a scp=1.0v under voltage lock out uvlo threshold voltage vuvlo 5.6 5.7 5.8 v vcc sweep down hysteresis voltage range dvuvlo 0.05 0.1 0.15 v 20/28 pin description pinno/pinname (bd9775fv) (bd9775fv) block diagram (bd9775fv) fig.1 function explanation (bd9775fv) 1.dc/dc converter ? reference voltage stable voltage of compensated temperature, is generated from the power supply volt age (vcc). the reference voltage is 3.0v, the accuracy is 1 . place a capacitor with low esr (several decades m ) between vref and gnd. ? internal regulator a vrega 5v is generated the power supply voltage. the voltage is for t he driver of the synchronous re ctification?s mosfet. place a capacitor with low esr (several decades m ) between vrega and pgnd. pin no. pin name description 1 fb1 error amplifier output pin channel 1 2 inv1 error amplifier negative input pin channel 1 3 rt oscillator frequency adjustment pin connected resistor 4 ct oscillator frequency adjustment pin connected capacitor 5 fin oscillator synchroniza tion pulse signal input pin 6 gnd low-noise ground 7 vref reference voltage output pin 8 dtc1 maximum duty and soft start adjustment pin channel 1 9 dtc2 maximum duty and soft start adjustment pin channel 2 10 inv2 error amplifier negative input pin channel 2 11 fb2 error amplifier output pin channel 2 12 ctl1 enable/stand-by control input channel 1 13 ctl2 enable/stand-by control input channel 2 14 vcc main power supply pin 15 sync synchronous rectific ation timing adjustable pin 16 pgnd power ground (connected low-side gate driver and digital ground) 17 out2l low-side ( synchronous rectifier ) gate driver output pin channel 2 18 vrega connected capacitor for internal regulator 19 scp delay time of short circ uit protection adjustment pin connected capacitor 20 vs2 over current detection voltage monitor pin connected fet drain, channel 2 21 cl2 over current detection voltage adjustment pin connected capacitor and resistor channel 2 22 pvcc2 high-side gate driver power supply input channel 2 23 out2h high-side gate driver output pin channel 2 24 vregb connected capacitor for internal regulator 25 out1 high-side gate driver output pin channel 1 26 pvcc1 high-side gate driver power supply input channel 1 27 cl1 over current detection voltage adjustment pin connected capacitor and resistor channel 1 28 vs1 over current detection voltage monitor pin connected fet drain, channel 1 28 27 26 25 24 23 22 21 20 19 18 1 2 3 4 5 6 7 8 9 10 11 fb1 inv1 rt ct fin gnd vref dtc1 dtc2 inv2 fb2 vs1 cl1 pvcc1 out1 vregb out2h pvcc2 cl2 vs2 scp vrega 17 16 15 12 13 14 ctl1 ctl2 vcc out2l pgnd sync 21/28 ? internal regulator b vregb (vcc-5v) is generated from the power supply voltage. the vo ltage is for the driver of the main mosfet switch. place a capacitor with low esr (several decades m ) between vregb and pvcc. ? oscillator placing a resistor and a capacitor to rt and ct, respectively, generates two triangle waves for both cannels, and each wave is opposite phase. the waves are input to the pwm compar ators for ch1 and ch2. also, the oscillating frequency can be slightly adjusted (less than 20%) by putting external clock pulse into fin pin, which is higher frequency than the fixed one. ? error amplifier it amplifies the difference, between the es tablish output voltage and the actual out put one detected at inv. and amplified voltage comes out from fb. the comparing voltage is 1.0v and the accuracy is 2%. the phase can be compensated externally by placing a resistor and a capacitor between inv and fb. ? pwm comparator it converts the output voltage from error amplifier into pwm waveform, then output to mosfet driver. ? mosfet driver the main drivers (out1, out2h) are for p-channel mosfets, and the dr iver (out2l) for synchron ous rectification is for n-channel mosfet. the values of output voltage are clamp to vregb, vrega, respectively. all drivers? output configurations are push-pull type. in addition, the output current capability is 36ma for the sink current and 320ma (vds=0.4v) for the source current. 2.channel control each output can be individually turned on or off with ctl1 and ctl2. when the ctl is ?h? (mo re than 1.5v), it becomes turned on. 3.protection ? over current protection ocp when detected over current (detecting drop voltage of the main mosfet?s on resistance), the mosfet switch becomes turned off, and the energy on dtc pin is discharged. after disc harged, the output restarts aut omatically. the level of the ocp detection threshold can be set by the resistance, which is connected between vcc and cl. ? short circuit protection scp when either output goes down and the voltage on inv pin gets lower than 0.7v, a capacitor placed on scp is started to charge. when the scp pin becomes more than 2.0v, the main mosfet switches of both outputs are tu rned off; then, the outputs are latched. while they are latched, the ic can be rese t by restarting vcc or ctl, or discharging scp. ? under voltage lock out uvlo due to avoiding malfunctions when the ic is started up or t he power supply voltage is rapidly disconnected, the main mosfet switches become off and dtc is discharged when the su pply voltage is less than 5.7v. also, when the output is latched because of scp function, the latch becomes reset. due to preventing malfunctions in the case the power supply voltage fluctuate at near uvlo threshol d, there is 0.1v hysteresis between the detection and reset voltage of uvlo threshold. ? thermal shut down tsd due to preventing breakdown of the ic by heating up, the main mosf et switches become off and dtc pin is discharged by detecting over temperature of the chip. due to preventing malfunctions in the case temperature fluctuate at near tsd threshold, there is hysteresis between tsd on and off. 22/28 setting up infomation (bd9775fv) 1)simultaneously off duty of mosf ets for synchronous rectification the simultaneously off duty of both main mosfet switch and synchronous rectification mosfet is determined by resistance (rsync) between sync and gnd. see fig. 4. in synchronous rectification, insert rfb2-gnd (rfb2-gnd P 3 rsync) between fb2 and gnd, because it is possible to reduce overshoot(sea fig.2). rfb2-gnd decide following formula. fig.2 ? resistance at fb2-gnd setup condition rsync(max) max dispersion range at rsync rsync(min) min dispersion range at rsync short sync to vref if the synchronous re ctification function is not needed. without synchronous rectification don?t insert r fb2-gnd 0 5 10 15 20 25 30 35 40 0 20406080100 rsync (k) duty (%) t=-40 t= 25 t=105 sync vref fosc=100khz duty=(t1+t2)/t 100 (% ) out2h out2l t1 t2 t threshold voltage at100% -out p ut source current at fb2 vsync 3 rsync(max) < r fb2-gnd < 3xrsync(min) 2.08 0.4908 rsync(max) + 80.7x10 -6 r fb2-gnd < < 3xrsync(min) rsync sync fb2 r fb2-gnd 23/28 2) oscillator synchronization by external pulse signal at the operation the oscillator is externally synchronized, input the synchronization signal into fin in addition to connect a resistor and a capacitor at rt and ct, respectively. input the external clock pulse on fin, which is higher fre quency than the fixed one. however, the frequency variation should be less than 20%. also, the duty cycle of the pulse should be set from 10% to 90%. ct waveform during synchronized with external pulse short fin to gnd if the function of exte rnal synchronization is not needed. without synchronization signal 3)setting the over current threshold level the ocp detection level iocp is determined by the on resistance (r on ) of the main mosfet switch and the resistance (rcl) which is placed between cl and vcc. iocp 10 -5 [a] typ. to prevent a malfunction caused by noise, place a capacitor ccl parallel to rcl. if ocp function is not needed, short vs to vcc, and short cl to gnd. with ocp without ocp cl, vs pin connection rcl r o n fin fin ct fixed with rt and ct synchronized cl vs vcc cl vs rcl vcc ccl to main mosfet drain 24/28 4)setting the time for short circuit protection the time (tscp) from output short to latch activation is de termined by the capacitor, cscp, connected scp pin. tscp 7.96 10 5 cscp [sec] typ. short scp to gnd if scp function is not being used. without scp 5)single channel operation this device can be used as a single output. the connection is as follows; dtc,fb,ctl,cl short to gnd vs,pvcc short to vcc inv short to vref single channel operation 6)setting the oscillating frequency the oscillating frequency can be set by selecting t he timing resistor (rrt)and the timing capacitor (cct). fig.3 fig.4 ocsillating freq uency vs. timing capacitance (cct) 10 100 1000 10 100 1000 timing resistance (k) oscillating frequency (khz) c ct =470pf c ct =1000pf c ct =100pf scp ocsillating frequency vs. timing capacitance (rrt) 10 100 1000 100 1000 10000 timing capacitance(pf) oscillating frequency (khz) r rt =100k r rt =27k r rt =5.1k dtc fb ctl cl vs pvcc inv vref vcc 25/28 timing chart (bd9775fv) ? output on/off, minimum input uvlo fig.5 ? over current protection, short circu it protection, thermal shut down fig.6 i/o equivalent circuit (bd9775fv) fb1(1) fb2(11) rt(3) vref vrega vcc fb1 vref vrega vcc vref rt vcc inv1(2),inv2(10) ct(4) fin(5) vcc vref inv1,2 vref vcc vreg vcc fin fig.8 fi g .7 vcc ctl1 ctl2 dtc1 dtc2 vout1 vout2 6.0v uvlo is inactivated at 5.8v stand-by soft start 1.0v 1.0 v uvlo is activated at 5.7v ctl1,2 scp dtc1,2 vout1,2 iout1,2 ocp is activated by detecting 8 consecutive cycles ocp detection level 1.0v 2.0v half short of output a ctivate scp inactivate half-short reset the latch by restarting ctl a ctivate tsd inactivate tsd 0.7 fixed output voltage vcc fb1 vreg a vref vcc vreg a vref vcc vref inv1 2 vcc vref vcc vref rt vcc vref fin 26/28 dtc1(8),dtc2(9) ctl1(12),ctl2(13) sync(15) vrega vref dtc1,2 vcc vcc vrega ctl1,2 vref vcc sync scp(19) out2l(17),vrega(18) vref(7) vcc scp vref vcc vrega out2l d> d> vref vc pvcc1(26),pvcc2(22) out1(25),out2h(23),vregb(24) vs1(28),vs2(20),cl1(27),cl2(21) vcc pvcc1,2 out1,2h vregb cl1,2 v s1,2 v cc operation notes (bd9775fv) 1) absolute maximum ratings use of the ic in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in ic deterioration or damage. assumptions should not be made regarding the state of the ic (short mode or open mode) when such damage is suffered. a physical safety measure such as a fuse should be implemented w hen use of the ic in a special mode where the absolute maximum ratings may be exceeded is anticipated. 2) gnd potential ensure a minimum gnd pin potential in a ll operating conditions. in additi on, ensure that no pins other than the gnd pin carry a voltage lower than or equal to the gnd pin, incl uding during actual transient phenomena. 3) thermal design use a thermal design that allows for a sufficient margin in li ght of the power dissipation (pd) in actual operating conditions. 4) inter-pin shorts and mounting errors use caution when orienting and positioning t he ic for mounting on printed circuit boards . improper mounting may result in damag e to the ic. shorts between output pins or between output pins and the power s upply and gnd pin caused by the presence of a foreign object m ay result in damage to the ic. 5) operation in a strong electromagnetic field use caution when using the ic in the pr esence of a strong electromagnetic field as doing so may cause the ic to malfunction. 6) thermal shutdown ci rcuit (tsd circuit) this ic incorporates a built-in thermal shutdown circuit (tsd circuit). the tsd circ uit is designed only to shut the ic off to prevent runaway thermal operation. do not continue to use the ic after operati ng this circuit or use the ic in an environment where the operati on of the thermal shutdown circuit is assumed. 7) testing on application boards when testing the ic on an application board, connecting a capacitor to a pin with low impedance subjects the ic to stress. alwa ys discharge capacitors after each process or step. ground the ic during asse mbly steps as an antistatic measure, and use similar caution wh en transporting or storing the ic. always turn the ic's power supply off before connecting it to or removing it from a jig or fixt ure during the inspection process. 8) common impedance power supply and ground wiring should reflect consideration of the need to lower comm on impedance and minimize ripple as much a s possible (by making wiring as short and thick as possible or rejecting ripple by inco rporating inductance and capacitance). fi g .8 vcc vrega vref dtc1,2 vcc vref scp vcc pvcc1 2 outh1 2h vregb vcc vs1 2 cl1 2 vcc vref vcc vrega out2l vcc vrega ctl1 2 vref vcc sync 27/28 vcc pin bypass diode countercurrent prevention diode 9) applications with modes that re verse vcc and pin potentials may cause damage to internal ic circuits. for example, such damage might occur when vcc is shorted with the gnd pin while an external capacitor is charged. it is recommended to insert a diode for preventing back current flow in series with vcc or bypass diodes between vcc and each pin. fig.9 10) timing resistor and capacitor timing resistor(capacitor) connected between rt(ct) and gnd, has to be placed near rt(ct) termi nal 3pin(4pin). and pattern has to be short enough. 11) the dead time input voltage has to be set more than 1.1v. also, the resistance between dtc and vref is used more than 30k ? to work ocp function reliably. 12) the energy on dtc1 8pin and dtc2 9pin is discharged when ctl1 12pin and ctl2 13pin are off, respectively, or vcc 14pin is off (uvlo activation). however, it is considerable to occur overshoot when ctl and vcc are turned on with remaining more th an 1v on the dtc. 13) if gate capacitance of p-channel mosfet or resistance placed on gate is large, and the time from beginning of gate switching to the end of drain?s (tsw), is long, it may not start up due to the ocp malfunction. to avoid it, select mosfet or adjust resistance as tsw becomes less than 270nsec. fig.10 14) ic pin input this monolithic ic contains p+ isolat ion and pcb layers between adjacent elements in order to keep them isolated. p/n junctions are formed at the intersecti on of these p layers with the n layers of other elements to create a variety of parasitic elements. for example, when a resistor and trans istor are connected to pins as shown in following chart, the p/n junction functions as a parasitic diode when gnd > (pin a) for the resistor or gnd > (pin b) for the transistor (npn). similarly, when gnd > (pin b) for the transistor (npn), the pa rasitic diode described above combines with the n layer of other adjacent elements to operate as a parasitic npn transistor. the formation of parasitic elements as a result of the re lationships of the potentials of different pins is an inevitable result of the ic's architecture. the operation of parasitic elements can cause interference with circuit operation as well as ic malfunction and damag e. for these reasons, it is necessary to use caution so that the ic is not used in a way that will trigger the operation of parasiti c elements, such as by the application of voltages lower than the gnd (pcb) voltage to input and output pins. fig.11 fig.12 tsw gate drain copper laminate area 70 mm70mm with no heat sink 0.4 0.6 0.2 0 50 75 100 125 0 25 ambient temperature ta( ) pd(w) 0.8 0.587w 0.64w power dissipation pd( w 1.0 0.85w 150 n p + (pina) resistor parasitic element p p + gnd p n (pinb) transistor npn p + p + n n p substrate gnd n p c e b parasitic element or transistor gnd c b parasitic element or transisto r (pinb) e (pina) parasitic element 28/28 part order number b d 9 7 7 5 f v - e 2 rohm part code type/no. package type tape and reel information ssop-b28 ( unit:mm ) ssop-b28 notes no technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of rohm co.,ltd. the contents described herein are subject to change without notice. the specifications for the product described in this document are for reference only. upon actual use, therefore, please request that specifications to be separately delivered. application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. rohm co.,ltd. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by rohm co., ltd. is granted to any such buyer. products listed in this document are no antiradiation design. appendix1-rev2.0 thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact your nearest sales office. rohm customer support system the americas / europe / asia / japan contact us : webmaster@ rohm.co. jp www.rohm.com copyright ? 2008 rohm co.,ltd. the products listed in this document are designed to be used with ordinary electronic equipment or de vices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of which would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. it is our top priority to supply products with the utmost quality and reliability. however, there is always a chance of failure due to unexpected factors. therefore, please take into account the derating characteristics and allow for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in order to prevent possible accidents that may result in bodily harm or fire caused by component failure. rohm cannot be held responsible for any damages arising from the use of the products under conditions out of the range of the specifications or due to non-compliance with the notes specified in this catalog. 21 saiin mizosaki- cho, ukyo-ku, kyoto 615-8585, japan tel : +81-75-311-2121 fax : +81-75-315-0172 appendix |
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